; Generated by holtek-gcc v3.20, Fri Aug 28 11:30:23 2020
; 
; Configuration:
;       with long instruction
;       Multi-ROM, Multi-RAM
;       bits_per_rom_unit:16
;       with mp1
;       with tbhp, address(0x9)
;          Use tabrd-const
;       
; SFR address of long-instruction arch:
;    mp0 = -1,1,0
;    mp1 = 4,3,2
;    mp2 = 14,13,12
;    tbp = 9,7,8
;    acc = 5
;    pcl = 6
;    status = 10
;    bp = 11
;    intc = 16
;       
;       
; use 'tabrdc' instead of 'tabrd'
;       

#pragma translator "holtek-gcc 4.6.4" "3.20" "build 20130711"
; Rebuild 610

ir equ [2]
mp equ [3]
sbp equ [4]
acc equ [5]
bp equ [11]
tblp equ [7]
tbhp equ [9]
status equ [10]
c equ [10].0
ac equ [10].1
z equ [10].2
ov equ [10].3
cz equ [10].6
sc equ [10].7
intc equ [16]
mduwr0 equ [59h]
mduwr1 equ [5ah]
mduwr2 equ [5bh]
mduwr3 equ [5ch]
mduwr4 equ [5dh]
mduwr5 equ [5eh]
mduwrctrl equ [5fh]

extern ra:byte
extern rb:byte
extern rc:byte
extern rd:byte
extern re:byte
extern rf:byte
extern rg:byte
extern rh:byte
extern _Crom2Prom:near
extern _Crom2PromNext:near

RAMBANK 0 @BITDATASEC, @BITDATASEC1
@HCCINIT	.section 'data'
@HCCINIT0	.section 'data'
@BITDATASEC	 .section 'data'
@BITDATASEC1	 .section 'data'

#pragma debug scope 1 1
	extern __DELAY3:near
	extern __DELAYX3:near
	extern __DELAYX6:near
	extern __DELAYY5:near
	extern __DELAYY3:near
	extern _builtin_holtek_delay_2:byte
___u0cr1 equ [275]
___u0cr2 equ [276]
___brdl0 equ [278]
___brdh0 equ [277]
___ufcr0 equ [279]
___mfi5 equ [75]
___u0sr equ [274]
___intc3 equ [19]
___intc0 equ [16]
___pas1 equ [335]
___ifs4 equ [333]
public _Drv_UART0_Init
#pragma debug scope 2 1
#line 24 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
_Drv_UART0_Init .section 'code'
_Drv_UART0_Init proc
#line 25 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
	lclr [275]
	lclr [276].5
#line 26 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
	mov a,65
	lmov [278],a
	mov a,3
	lmov [277],a
	mov a,24
	lmov [279],a
#line 27 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
	lclr [279].1
	lset [279].0
#line 28 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
	lclr [276].4
#line 29 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
	lset [276].2
#line 30 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
	lset [276].1
#line 31 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
	lset [276].0
#line 32 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
	lset [275].7
	lset [276].6
	lset [276].7
	clr [75].4
	lclr [274].0
	set [75].0
	clr [19].7
	set [19].3
	set [16].0
#line 33 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
	set [16].0
#line 35 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
	lset [335].5
	lclr [335].4
	lclr [333].0
#line 36 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
	lset [335].7
	lclr [335].6
#line 37 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
	mov a,3
	mov _DrvUart0Format[115],a
	ret
_Drv_UART0_Init endp
#line 37 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
#pragma debug scope 1 1
___acc equ [5]
___txr_rxr0 equ [280]
public _Drv_Uart0StartTx
#pragma debug scope 3 1
#line 41 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
_Drv_Uart0StartTx .section 'code'
_Drv_Uart0StartTx proc
    local _Drv_Uart0StartTx_2 db 1 dup(?)	; 0,1
	mov ra,a
	mov _Drv_Uart0StartTx_2[0],a
#pragma debug variable 8 3 _Drv_Uart0StartTx_2+0 "TxLength"
#line 42 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
	mov a,ra
	mov _DrvUart0Format[114],a
#line 44 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
	set _DrvUart0Format[116].0
#line 45 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
	clr _DrvUart0Format[110]
#line 46 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
	lmov a,[274]
	mov [5],a
#line 47 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
	mov a,_DrvUart0Format[0]
	lmov [280],a
	ret
_Drv_Uart0StartTx endp
#line 47 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
#pragma debug scope 1 1
___u1cr1 equ [322]
___u1cr2 equ [323]
___brdl1 equ [325]
___brdh1 equ [324]
___ufcr1 equ [326]
___u1sr equ [321]
___pfs1 equ [345]
public _Drv_UART1_Init
#pragma debug scope 4 1
#line 51 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
_Drv_UART1_Init .section 'code'
_Drv_UART1_Init proc
#line 52 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
	lclr [322]
	lclr [323].5
#line 53 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
	mov a,65
	lmov [325],a
	mov a,3
	lmov [324],a
	mov a,24
	lmov [326],a
#line 54 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
	lclr [326].1
	lset [326].0
#line 55 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
	lclr [323].4
#line 56 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
	lset [323].2
#line 57 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
	lset [323].1
#line 58 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
	lset [323].0
#line 59 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
	lset [322].7
	lset [323].6
	lset [323].7
	clr [75].5
	lclr [321].0
	set [75].1
	clr [19].7
	set [19].3
	set [16].0
#line 60 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
	set [16].0
#line 62 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
	lclr [345].5
	lset [345].4
	lset [333].1
#line 63 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
	lset [345].7
	lclr [345].6
#line 64 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
	mov a,2
	mov _DrvUart1Format[115],a
	ret
_Drv_UART1_Init endp
#line 64 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
#pragma debug scope 1 1
___txr_rxr1 equ [327]
public _Drv_Uart1StartTx
#pragma debug scope 5 1
#line 68 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
_Drv_Uart1StartTx .section 'code'
_Drv_Uart1StartTx proc
    local _Drv_Uart1StartTx_2 db 1 dup(?)	; 0,1
	mov ra,a
	mov _Drv_Uart1StartTx_2[0],a
#pragma debug variable 8 5 _Drv_Uart1StartTx_2+0 "TxLength"
#line 69 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
	mov a,ra
	mov _DrvUart1Format[114],a
#line 71 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
	set _DrvUart1Format[116].0
#line 72 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
	clr _DrvUart1Format[110]
#line 73 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
	lmov a,[321]
	mov [5],a
#line 74 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
	mov a,_DrvUart1Format[0]
	lmov [327],a
	ret
_Drv_Uart1StartTx endp
#line 74 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
#pragma debug scope 1 1
___rxcnt0 equ [281]
___rxcnt1 equ [328]
public _USIM0_ISR
#pragma debug scope 6 1
#line 78 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
rombank 0 @USIM0_ISR_code
@USIM0_ISR_code .section at 60 'code'
	mov r1,a
	mov a,bp
	clr bp
	jmp _USIM0_ISR
ROMBANK 0 _USIM0_ISR
#pragma debug scope 1 1
@dummy60 proc
	call _USIM0_ISR
@dummy60 endp
#pragma debug scope 7 1
_USIM0_ISR .section 'code'
_USIM0_ISR proc
	mov r2,a
	mov a, status
	mov r3,a
	mov a,mp
	mov r4,a
	mov a,sbp
	mov r5,a
	mov a,tblp
	mov r6,a
	mov a,tbhp
	mov r7,a
#line 79 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
	snz [75].4
	jmp _L6
#line 81 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
	clr [75].4
#line 89 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
	clr ra
	lsz [274].6
	inc ra
	clr rc
	lsz [274].5
	inc rc
	clr rb
	lsz [274].4
	inc rb
	mov a,rc
	orm a,ra
	mov a,rb
	orm a,ra
	snz ra
	jmp _L7
#line 91 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
	lmov a,[274]
	mov [5],a
#line 92 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
	lmov a,[280]
	mov [5],a
#line 93 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
	clr _DrvUart0Format[111]
_L7:
#line 96 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
	lsnz [274].0
	jmp _L9
	snz _DrvUart0Format[116].0
	jmp _L9
#line 101 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
	inc _DrvUart0Format[110]
#line 102 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
	mov a,_DrvUart0Format[110]
	sub a,_DrvUart0Format[114]
	sz c
	jmp _L11
#line 104 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
	mov a,low offset _DrvUart0Format
	add a,_DrvUart0Format[110]
	mov mp,a
	mov a,high offset _DrvUart0Format
	clr sbp
	adcm a,sbp
	fcall _Crom2Prom
	lmov [280],a
	jmp _L9
_L11:
#line 108 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
	lsnz [274].1
	jmp _L9
#line 110 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
	set _Txfinish_flag
#line 111 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
	clr _DrvUart0Format[116].0
_L9:
#line 117 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
	lsnz [274].2
	jmp _L5
_L40:
#line 121 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
	mov a,low (offset _DrvUart0Format+100)
	add a,_DrvUart0Format[111]
	mov mp,a
	mov a,high (offset _DrvUart0Format+100)
	clr sbp
	adcm a,sbp
	lmov a,[280]
	mov ir,a
#line 122 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
	clr _DrvUart0Format[112]
#line 123 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
	inc _DrvUart0Format[111]
#line 124 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
	lsz [281]
	jmp _L40
#line 135 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
	mov a,_DrvUart0Format[111]
	sub a,_DrvUart0Format[115]
	snz c
	jmp _L5
#line 137 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
	clr _DrvUart0Format[111]
#line 138 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
	mov a,3
	mov _DrvUart0Format[115],a
#line 139 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
	set _DrvUart0Format[116].1
	jmp _L5
_L6:
#line 144 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
	snz [75].5
	jmp _L5
#line 146 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
	clr [75].5
#line 154 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
	clr ra
	lsz [321].6
	inc ra
	clr rc
	lsz [321].5
	inc rc
	clr rb
	lsz [321].4
	inc rb
	mov a,rc
	orm a,ra
	mov a,rb
	orm a,ra
	snz ra
	jmp _L17
#line 156 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
	lmov a,[321]
	mov [5],a
#line 157 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
	lmov a,[327]
	mov [5],a
#line 158 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
	clr _DrvUart1Format[111]
_L17:
#line 161 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
	lsnz [321].0
	jmp _L19
	snz _DrvUart1Format[116].0
	jmp _L19
#line 164 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
	inc _DrvUart1Format[110]
#line 165 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
	mov a,_DrvUart1Format[110]
	sub a,_DrvUart1Format[114]
	sz c
	jmp _L21
#line 167 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
	mov a,low offset _DrvUart1Format
	add a,_DrvUart1Format[110]
	mov mp,a
	mov a,high offset _DrvUart1Format
	clr sbp
	adcm a,sbp
	fcall _Crom2Prom
	lmov [327],a
	jmp _L19
_L21:
#line 171 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
	lsnz [321].1
	jmp _L19
#line 173 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
	clr _DrvUart1Format[116].0
_L19:
#line 178 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
	lsnz [321].2
	jmp _L5
_L23:
#line 182 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
	mov a,low (offset _DrvUart1Format+100)
	add a,_DrvUart1Format[111]
	mov mp,a
	mov a,high (offset _DrvUart1Format+100)
	clr sbp
	adcm a,sbp
	lmov a,[327]
	mov ir,a
#line 183 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
	clr _DrvUart1Format[112]
#line 184 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
	inc _DrvUart1Format[111]
#line 185 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
	lsz [328]
	jmp _L23
#line 196 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
	mov a,_DrvUart1Format[111]
	sub a,_DrvUart1Format[115]
	snz c
	jmp _L5
#line 198 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
	clr _DrvUart1Format[111]
#line 199 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
	mov a,2
	mov _DrvUart1Format[115],a
#line 200 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
	set _DrvUart1Format[116].1
_L5:
	mov a,r2
	mov bp,a
	mov a,r3
	mov status,a
	mov a,r4
	mov mp,a
	mov a,r5
	mov sbp,a
	mov a,r6
	mov tblp,a
	mov a,r7
	mov tbhp,a
	tabrdc acc
	mov a,r1
	reti
_USIM0_ISR endp

#line 200 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
#pragma debug scope 1 1
public _Drv_UART0WriteTxBuf
#pragma debug scope 8 1
#line 219 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
_Drv_UART0WriteTxBuf .section 'code'
_Drv_UART0WriteTxBuf proc
public _Drv_UART0WriteTxBuf_2
    local _Drv_UART0WriteTxBuf_2 db 4 dup(?)	; 4,0
#pragma debug pointer 42 7 8
#pragma debug variable 42 8 _Drv_UART0WriteTxBuf_2+0 "src"
#pragma debug variable 8 8 _Drv_UART0WriteTxBuf_2+2 "startaddr"
#pragma debug variable 8 8 _Drv_UART0WriteTxBuf_2+3 "len"
#line 220 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
	mov a,_Drv_UART0WriteTxBuf_2[2]
	mov rb,a
	clr rc
	mov a,_Drv_UART0WriteTxBuf_2[3]
	addm a,rb
	sz c
	inc rc
	mov a,100
	sub a,rb
	mov a,0
	sbc a,rc
	sz sc
	jmp _L54
	mov a,_Drv_UART0WriteTxBuf_2[0]
	mov rb,a
	mov a,_Drv_UART0WriteTxBuf_2[1]
	mov rc,a
_L52:
#pragma debug scope 9 8
;begin block, line: 220.-1
#line 227 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
	mov a,_Drv_UART0WriteTxBuf_2[2]
	sub a,_Drv_UART0WriteTxBuf_2[3]
	sz c
	jmp _L55
#line 229 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
	mov a,rb
	mov mp,a
	mov a,rc
	mov sbp,a
	fcall _Crom2Prom
	mov ra,a
	mov a,low offset _DrvUart0Format
	add a,_Drv_UART0WriteTxBuf_2[2]
	mov mp,a
	mov a,high offset _DrvUart0Format
	clr sbp
	adcm a,sbp
	mov a,ra
	mov ir,a
#line 227 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
	inc _Drv_UART0WriteTxBuf_2[2]
	inc rb
	sz z
	inc rc
	jmp _L52
_L55:
#line 231 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
	clr ra
	jmp _L51
_L54:
#pragma debug scope 8 1
#line 222 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
	mov a,2
	mov ra,a
_L51:
#line 233 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
	mov a,ra
	ret
_Drv_UART0WriteTxBuf endp
#line 233 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
#pragma debug scope 1 1
public _Drv_UART1WriteTxBuf
#pragma debug scope 10 1
#line 244 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
_Drv_UART1WriteTxBuf .section 'code'
_Drv_UART1WriteTxBuf proc
public _Drv_UART1WriteTxBuf_2
    local _Drv_UART1WriteTxBuf_2 db 4 dup(?)	; 4,0
#pragma debug pointer 43 7 10
#pragma debug variable 43 10 _Drv_UART1WriteTxBuf_2+0 "src"
#pragma debug variable 8 10 _Drv_UART1WriteTxBuf_2+2 "startaddr"
#pragma debug variable 8 10 _Drv_UART1WriteTxBuf_2+3 "len"
#line 245 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
	mov a,_Drv_UART1WriteTxBuf_2[2]
	mov rb,a
	clr rc
	mov a,_Drv_UART1WriteTxBuf_2[3]
	addm a,rb
	sz c
	inc rc
	mov a,100
	sub a,rb
	mov a,0
	sbc a,rc
	sz sc
	jmp _L60
	mov a,_Drv_UART1WriteTxBuf_2[0]
	mov rb,a
	mov a,_Drv_UART1WriteTxBuf_2[1]
	mov rc,a
_L58:
#pragma debug scope 11 10
;begin block, line: 245.-1
#line 252 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
	mov a,_Drv_UART1WriteTxBuf_2[2]
	sub a,_Drv_UART1WriteTxBuf_2[3]
	sz c
	jmp _L61
#line 254 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
	mov a,rb
	mov mp,a
	mov a,rc
	mov sbp,a
	fcall _Crom2Prom
	mov ra,a
	mov a,low offset _DrvUart1Format
	add a,_Drv_UART1WriteTxBuf_2[2]
	mov mp,a
	mov a,high offset _DrvUart1Format
	clr sbp
	adcm a,sbp
	mov a,ra
	mov ir,a
#line 252 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
	inc _Drv_UART1WriteTxBuf_2[2]
	inc rb
	sz z
	inc rc
	jmp _L58
_L61:
#line 256 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
	clr ra
	jmp _L57
_L60:
#pragma debug scope 10 1
#line 247 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
	mov a,2
	mov ra,a
_L57:
#line 258 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
	mov a,ra
	ret
_Drv_UART1WriteTxBuf endp
#line 258 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
#pragma debug scope 1 1
public _Txfinish_flag
@HCCINIT	.section 'data'
#line 22 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
@BITDATASEC .section 'data'
_Txfinish_flag	dbit 0
#pragma debug variable 2 1 _Txfinish_flag "Txfinish_flag"
#line 21 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
public _DrvUart1Format
@HCCINIT0_DrvUart1Format .section 'data'
_DrvUart1Format	db 117 dup(0)
#pragma debug struct_begin 44 ""
#pragma debug field 21 8 0 1 "IsBusyTx" ;0,1
#pragma debug field 21 8 0 1 "IsRxSuccess" ;1,1
#pragma debug struct_end
#pragma debug union_begin 45 ""
#pragma debug field 2 44 "b"
#pragma debug field 0 8 "byte"
#pragma debug union_end
#pragma debug struct_begin 46 "DrvUartFormat_t"
#pragma debug field 1 8 100 "TxBuf"
#pragma debug field 1 8 10 "RxBuf"
#pragma debug field 0 8 "TxBufoffset"
#pragma debug field 0 8 "RxBufoffset"
#pragma debug field 0 8 "RxTimeOutCnt"
#pragma debug field 0 8 "TxCycle"
#pragma debug field 0 8 "TxLength"
#pragma debug field 0 8 "RxLength"
#pragma debug field 3 45 "flag"
#pragma debug struct_end
#pragma debug variable 46 1 _DrvUart1Format "DrvUart1Format"

@HCCINIT .section 'data'
#line 20 "c:\users\iris\desktop\2. demo code\bh67f5362_uart\BH67F5362_Drv\Drv_UART.c"
public _DrvUart0Format
@HCCINIT0_DrvUart0Format .section 'data'
_DrvUart0Format	db 117 dup(0)
#pragma debug variable 46 1 _DrvUart0Format "DrvUart0Format"

@HCCINIT .section 'data'
#pragma debug variable 8 1 ___acc "__acc" 1
#pragma debug struct_begin 47 "__intc0_bits"
#pragma debug field 21 8 0 1 "__emi" ;0,1
#pragma debug field 21 8 0 1 "__int0e" ;1,1
#pragma debug field 21 8 0 1 "__int1e" ;2,1
#pragma debug field 21 8 0 1 "__mf6e" ;3,1
#pragma debug field 21 8 0 1 "__int0f" ;4,1
#pragma debug field 21 8 0 1 "__int1f" ;5,1
#pragma debug field 21 8 0 1 "__mf6f" ;6,1
#pragma debug field 21 8 0 1 ;7,1
#pragma debug struct_end
#pragma debug union_begin 48 ""
#pragma debug field 2 47 "bits"
#pragma debug field 0 8 "byte"
#pragma debug union_end
#pragma debug variable 48 1 ___intc0 "__intc0" 1
#pragma debug struct_begin 49 "__intc3_bits"
#pragma debug field 21 8 0 1 "__int2e" ;0,1
#pragma debug field 21 8 0 1 "__int3e" ;1,1
#pragma debug field 21 8 0 1 "__mf4e" ;2,1
#pragma debug field 21 8 0 1 "__mf5e" ;3,1
#pragma debug field 21 8 0 1 "__int2f" ;4,1
#pragma debug field 21 8 0 1 "__int3f" ;5,1
#pragma debug field 21 8 0 1 "__mf4f" ;6,1
#pragma debug field 21 8 0 1 "__mf5f" ;7,1
#pragma debug struct_end
#pragma debug union_begin 50 ""
#pragma debug field 2 49 "bits"
#pragma debug field 0 8 "byte"
#pragma debug union_end
#pragma debug variable 50 1 ___intc3 "__intc3" 1
#pragma debug struct_begin 51 "__mfi5_bits"
#pragma debug field 21 8 0 1 "__ur0e" ;0,1
#pragma debug field 21 8 0 1 "__ur1e" ;1,1
#pragma debug field 21 8 0 2 ;2,2
#pragma debug field 21 8 0 1 "__ur0f" ;4,1
#pragma debug field 21 8 0 1 "__ur1f" ;5,1
#pragma debug field 21 8 0 2 ;6,2
#pragma debug struct_end
#pragma debug union_begin 52 ""
#pragma debug field 2 51 "bits"
#pragma debug field 0 8 "byte"
#pragma debug union_end
#pragma debug variable 52 1 ___mfi5 "__mfi5" 1
#pragma debug struct_begin 53 "__u0sr_bits"
#pragma debug field 21 8 0 1 "__txif0" ;0,1
#pragma debug field 21 8 0 1 "__tidle0" ;1,1
#pragma debug field 21 8 0 1 "__rxif0" ;2,1
#pragma debug field 21 8 0 1 "__ridle0" ;3,1
#pragma debug field 21 8 0 1 "__oerr0" ;4,1
#pragma debug field 21 8 0 1 "__ferr0" ;5,1
#pragma debug field 21 8 0 1 "__nf0" ;6,1
#pragma debug field 21 8 0 1 "__perr0" ;7,1
#pragma debug struct_end
#pragma debug union_begin 54 ""
#pragma debug field 2 53 "bits"
#pragma debug field 0 8 "byte"
#pragma debug union_end
#pragma debug variable 54 1 ___u0sr "__u0sr" 1
#pragma debug struct_begin 55 "__u0cr1_bits"
#pragma debug field 21 8 0 1 "__tx80" ;0,1
#pragma debug field 21 8 0 1 "__rx80" ;1,1
#pragma debug field 21 8 0 1 "__txbrk0" ;2,1
#pragma debug field 21 8 0 1 "__prt00" ;3,1
#pragma debug field 21 8 0 1 "__prt01" ;4,1
#pragma debug field 21 8 0 1 "__pren0" ;5,1
#pragma debug field 21 8 0 1 "__bno0" ;6,1
#pragma debug field 21 8 0 1 "__uarten0" ;7,1
#pragma debug struct_end
#pragma debug union_begin 56 ""
#pragma debug field 2 55 "bits"
#pragma debug field 0 8 "byte"
#pragma debug union_end
#pragma debug variable 56 1 ___u0cr1 "__u0cr1" 1
#pragma debug struct_begin 57 "__u0cr2_bits"
#pragma debug field 21 8 0 1 "__teie0" ;0,1
#pragma debug field 21 8 0 1 "__tiie0" ;1,1
#pragma debug field 21 8 0 1 "__rie0" ;2,1
#pragma debug field 21 8 0 1 "__wake0" ;3,1
#pragma debug field 21 8 0 1 "__adden0" ;4,1
#pragma debug field 21 8 0 1 "__stops0" ;5,1
#pragma debug field 21 8 0 1 "__rxen0" ;6,1
#pragma debug field 21 8 0 1 "__txen0" ;7,1
#pragma debug struct_end
#pragma debug union_begin 58 ""
#pragma debug field 2 57 "bits"
#pragma debug field 0 8 "byte"
#pragma debug union_end
#pragma debug variable 58 1 ___u0cr2 "__u0cr2" 1
#pragma debug variable 8 1 ___brdh0 "__brdh0" 1
#pragma debug variable 8 1 ___brdl0 "__brdl0" 1
#pragma debug struct_begin 59 "__ufcr0_bits"
#pragma debug field 21 8 0 1 "__rxftr00" ;0,1
#pragma debug field 21 8 0 1 "__rxftr01" ;1,1
#pragma debug field 21 8 0 1 "__brds0" ;2,1
#pragma debug field 21 8 0 1 "__umod00" ;3,1
#pragma debug field 21 8 0 1 "__umod01" ;4,1
#pragma debug field 21 8 0 1 "__umod02" ;5,1
#pragma debug field 21 8 0 2 ;6,2
#pragma debug struct_end
#pragma debug union_begin 60 ""
#pragma debug field 2 59 "bits"
#pragma debug field 0 8 "byte"
#pragma debug union_end
#pragma debug variable 60 1 ___ufcr0 "__ufcr0" 1
#pragma debug struct_begin 61 "__txr_rxr0_bits"
#pragma debug field 21 8 0 1 "__txrx00" ;0,1
#pragma debug field 21 8 0 1 "__txrx01" ;1,1
#pragma debug field 21 8 0 1 "__txrx02" ;2,1
#pragma debug field 21 8 0 1 "__txrx03" ;3,1
#pragma debug field 21 8 0 1 "__txrx04" ;4,1
#pragma debug field 21 8 0 1 "__txrx05" ;5,1
#pragma debug field 21 8 0 1 "__txrx06" ;6,1
#pragma debug field 21 8 0 1 "__txrx07" ;7,1
#pragma debug struct_end
#pragma debug union_begin 62 ""
#pragma debug field 2 61 "bits"
#pragma debug field 0 8 "byte"
#pragma debug union_end
#pragma debug variable 62 1 ___txr_rxr0 "__txr_rxr0" 1
#pragma debug variable 8 1 ___rxcnt0 "__rxcnt0" 1
#pragma debug struct_begin 63 "__u1sr_bits"
#pragma debug field 21 8 0 1 "__txif1" ;0,1
#pragma debug field 21 8 0 1 "__tidle1" ;1,1
#pragma debug field 21 8 0 1 "__rxif1" ;2,1
#pragma debug field 21 8 0 1 "__ridle1" ;3,1
#pragma debug field 21 8 0 1 "__oerr1" ;4,1
#pragma debug field 21 8 0 1 "__ferr1" ;5,1
#pragma debug field 21 8 0 1 "__nf1" ;6,1
#pragma debug field 21 8 0 1 "__perr1" ;7,1
#pragma debug struct_end
#pragma debug union_begin 64 ""
#pragma debug field 2 63 "bits"
#pragma debug field 0 8 "byte"
#pragma debug union_end
#pragma debug variable 64 1 ___u1sr "__u1sr" 1
#pragma debug struct_begin 65 "__u1cr1_bits"
#pragma debug field 21 8 0 1 "__tx81" ;0,1
#pragma debug field 21 8 0 1 "__rx81" ;1,1
#pragma debug field 21 8 0 1 "__txbrk1" ;2,1
#pragma debug field 21 8 0 1 "__prt10" ;3,1
#pragma debug field 21 8 0 1 "__prt11" ;4,1
#pragma debug field 21 8 0 1 "__pren1" ;5,1
#pragma debug field 21 8 0 1 "__bno1" ;6,1
#pragma debug field 21 8 0 1 "__uarten1" ;7,1
#pragma debug struct_end
#pragma debug union_begin 66 ""
#pragma debug field 2 65 "bits"
#pragma debug field 0 8 "byte"
#pragma debug union_end
#pragma debug variable 66 1 ___u1cr1 "__u1cr1" 1
#pragma debug struct_begin 67 "__u1cr2_bits"
#pragma debug field 21 8 0 1 "__teie1" ;0,1
#pragma debug field 21 8 0 1 "__tiie1" ;1,1
#pragma debug field 21 8 0 1 "__rie1" ;2,1
#pragma debug field 21 8 0 1 "__wake1" ;3,1
#pragma debug field 21 8 0 1 "__adden1" ;4,1
#pragma debug field 21 8 0 1 "__stops1" ;5,1
#pragma debug field 21 8 0 1 "__rxen1" ;6,1
#pragma debug field 21 8 0 1 "__txen1" ;7,1
#pragma debug struct_end
#pragma debug union_begin 68 ""
#pragma debug field 2 67 "bits"
#pragma debug field 0 8 "byte"
#pragma debug union_end
#pragma debug variable 68 1 ___u1cr2 "__u1cr2" 1
#pragma debug variable 8 1 ___brdh1 "__brdh1" 1
#pragma debug variable 8 1 ___brdl1 "__brdl1" 1
#pragma debug struct_begin 69 "__ufcr1_bits"
#pragma debug field 21 8 0 1 "__rxftr10" ;0,1
#pragma debug field 21 8 0 1 "__rxftr11" ;1,1
#pragma debug field 21 8 0 1 "__brds1" ;2,1
#pragma debug field 21 8 0 1 "__umod10" ;3,1
#pragma debug field 21 8 0 1 "__umod11" ;4,1
#pragma debug field 21 8 0 1 "__umod12" ;5,1
#pragma debug field 21 8 0 2 ;6,2
#pragma debug struct_end
#pragma debug union_begin 70 ""
#pragma debug field 2 69 "bits"
#pragma debug field 0 8 "byte"
#pragma debug union_end
#pragma debug variable 70 1 ___ufcr1 "__ufcr1" 1
#pragma debug struct_begin 71 "__txr_rxr1_bits"
#pragma debug field 21 8 0 1 "__txrx10" ;0,1
#pragma debug field 21 8 0 1 "__txrx11" ;1,1
#pragma debug field 21 8 0 1 "__txrx12" ;2,1
#pragma debug field 21 8 0 1 "__txrx13" ;3,1
#pragma debug field 21 8 0 1 "__txrx14" ;4,1
#pragma debug field 21 8 0 1 "__txrx15" ;5,1
#pragma debug field 21 8 0 1 "__txrx16" ;6,1
#pragma debug field 21 8 0 1 "__txrx17" ;7,1
#pragma debug struct_end
#pragma debug union_begin 72 ""
#pragma debug field 2 71 "bits"
#pragma debug field 0 8 "byte"
#pragma debug union_end
#pragma debug variable 72 1 ___txr_rxr1 "__txr_rxr1" 1
#pragma debug variable 8 1 ___rxcnt1 "__rxcnt1" 1
#pragma debug struct_begin 73 "__ifs4_bits"
#pragma debug field 21 8 0 1 "__rx0ps" ;0,1
#pragma debug field 21 8 0 1 "__rx1ps" ;1,1
#pragma debug field 21 8 0 6 ;2,6
#pragma debug struct_end
#pragma debug union_begin 74 ""
#pragma debug field 2 73 "bits"
#pragma debug field 0 8 "byte"
#pragma debug union_end
#pragma debug variable 74 1 ___ifs4 "__ifs4" 1
#pragma debug struct_begin 75 "__pas1_bits"
#pragma debug field 21 8 0 1 "__pas10" ;0,1
#pragma debug field 21 8 0 1 "__pas11" ;1,1
#pragma debug field 21 8 0 1 "__pas12" ;2,1
#pragma debug field 21 8 0 1 "__pas13" ;3,1
#pragma debug field 21 8 0 1 "__pas14" ;4,1
#pragma debug field 21 8 0 1 "__pas15" ;5,1
#pragma debug field 21 8 0 1 "__pas16" ;6,1
#pragma debug field 21 8 0 1 "__pas17" ;7,1
#pragma debug struct_end
#pragma debug union_begin 76 ""
#pragma debug field 2 75 "bits"
#pragma debug field 0 8 "byte"
#pragma debug union_end
#pragma debug variable 76 1 ___pas1 "__pas1" 1
#pragma debug struct_begin 77 "__pfs1_bits"
#pragma debug field 21 8 0 1 "__pfs10" ;0,1
#pragma debug field 21 8 0 1 "__pfs11" ;1,1
#pragma debug field 21 8 0 1 "__pfs12" ;2,1
#pragma debug field 21 8 0 1 "__pfs13" ;3,1
#pragma debug field 21 8 0 1 "__pfs14" ;4,1
#pragma debug field 21 8 0 1 "__pfs15" ;5,1
#pragma debug field 21 8 0 1 "__pfs16" ;6,1
#pragma debug field 21 8 0 1 "__pfs17" ;7,1
#pragma debug struct_end
#pragma debug union_begin 78 ""
#pragma debug field 2 77 "bits"
#pragma debug field 0 8 "byte"
#pragma debug union_end
#pragma debug variable 78 1 ___pfs1 "__pfs1" 1
extern r1:byte
extern r2:byte
extern r3:byte
extern r4:byte
extern r5:byte
extern r6:byte
extern r7:byte

; 
; Generated by holtek-gcc v3.20, Fri Aug 28 11:30:24 2020
; Rebuild 610
; end of file
