; Generated by holtek-gcc v3.20, Fri Aug 28 11:34:18 2020
; 
; Configuration:
;       with long instruction
;       Multi-ROM, Multi-RAM
;       bits_per_rom_unit:16
;       with mp1
;       with tbhp, address(0x9)
;          Use tabrd-const
;       
; SFR address of long-instruction arch:
;    mp0 = -1,1,0
;    mp1 = 4,3,2
;    mp2 = 14,13,12
;    tbp = 9,7,8
;    acc = 5
;    pcl = 6
;    status = 10
;    bp = 11
;    intc = 16
;       
;       
; use 'tabrdc' instead of 'tabrd'
;       

#pragma translator "holtek-gcc 4.6.4" "3.20" "build 20130711"
; Rebuild 610

ir equ [2]
mp equ [3]
sbp equ [4]
acc equ [5]
bp equ [11]
tblp equ [7]
tbhp equ [9]
status equ [10]
c equ [10].0
ac equ [10].1
z equ [10].2
ov equ [10].3
cz equ [10].6
sc equ [10].7
intc equ [16]
mduwr0 equ [59h]
mduwr1 equ [5ah]
mduwr2 equ [5bh]
mduwr3 equ [5ch]
mduwr4 equ [5dh]
mduwr5 equ [5eh]
mduwrctrl equ [5fh]

extern ra:byte
extern rb:byte
extern rc:byte
extern rd:byte
extern re:byte
extern rf:byte
extern rg:byte
extern rh:byte
extern _Crom2Prom:near
extern _Crom2PromNext:near

RAMBANK 0 @BITDATASEC, @BITDATASEC1
@HCCINIT	.section 'data'
@HCCINIT0	.section 'data'
@BITDATASEC	 .section 'data'
@BITDATASEC1	 .section 'data'

#pragma debug scope 1 1
	extern __DELAY3:near
	extern __DELAYX3:near
	extern __DELAYX6:near
	extern __DELAYY5:near
	extern __DELAYY3:near
	extern _builtin_holtek_delay_2:byte
___status equ [10]
___wdtc equ [62]
___lvrc equ [63]
public _main
#pragma debug scope 2 1
#line 14 "c:\users\iris\desktop\2. demo code\bh67f5362_24bit adc\Source\main.c"
IFDEF WITH_DEFAULT_STARTUP
extern _main_initial0:near
extern _main_startup:near
ENDIF

ROMBANK 0 @start
@start .section com_l 'code'
_main_startup1:
@start .section com_e 'code'
	mov a,bank _main
	mov bp,a
	jmp _main

_main .section 'code'
_main proc
    local _main_2 db 1 dup(?)
#line 17 "c:\users\iris\desktop\2. demo code\bh67f5362_24bit adc\Source\main.c"
	snz [10].5
	jmp _L2
#line 17 "c:\users\iris\desktop\2. demo code\bh67f5362_24bit adc\Source\main.c"
	sz [10].4
	jmp _L3
_L2:
#line 20 "c:\users\iris\desktop\2. demo code\bh67f5362_24bit adc\Source\main.c"
	fcall _Drv_SysClockInit
#line 21 "c:\users\iris\desktop\2. demo code\bh67f5362_24bit adc\Source\main.c"
	fcall _Drv_RamInit
#line 22 "c:\users\iris\desktop\2. demo code\bh67f5362_24bit adc\Source\main.c"
	mov a,82
	mov [62],a
#line 23 "c:\users\iris\desktop\2. demo code\bh67f5362_24bit adc\Source\main.c"
	mov a,85
	mov [63],a
#line 24 "c:\users\iris\desktop\2. demo code\bh67f5362_24bit adc\Source\main.c"
	fcall _Drv_UART0_Init
#line 26 "c:\users\iris\desktop\2. demo code\bh67f5362_24bit adc\Source\main.c"
	fcall _Drv_24BitADC_Init
#line 27 "c:\users\iris\desktop\2. demo code\bh67f5362_24bit adc\Source\main.c"
	fcall _Drv_24BitADC_Start
	jmp _L11
_L3:
#line 32 "c:\users\iris\desktop\2. demo code\bh67f5362_24bit adc\Source\main.c"
;# 32 "c:\users\iris\desktop\2. demo code\bh67f5362_24bit adc\Source\main.c" 1
	clr wdt
_L11:
#line 37 "c:\users\iris\desktop\2. demo code\bh67f5362_24bit adc\Source\main.c"
;# 37 "c:\users\iris\desktop\2. demo code\bh67f5362_24bit adc\Source\main.c" 1
	clr wdt
#line 38 "c:\users\iris\desktop\2. demo code\bh67f5362_24bit adc\Source\main.c"
	fcall _Drv_24BitADC_ReadADCData
#line 39 "c:\users\iris\desktop\2. demo code\bh67f5362_24bit adc\Source\main.c"
	snz _ADCSourceData[5].0
	jmp _L7
#pragma debug scope 3 2
;begin block, line: 39.-1
#line 41 "c:\users\iris\desktop\2. demo code\bh67f5362_24bit adc\Source\main.c"
	clr _ADCSourceData[5].0
#line 42 "c:\users\iris\desktop\2. demo code\bh67f5362_24bit adc\Source\main.c"
	mov a,162
	mov _DrvUart0Format[0],a
#line 43 "c:\users\iris\desktop\2. demo code\bh67f5362_24bit adc\Source\main.c"
	clr _DrvUart0Format[1]
#line 44 "c:\users\iris\desktop\2. demo code\bh67f5362_24bit adc\Source\main.c"
	mov a,_ADCSourceData[3]
	mov _DrvUart0Format[2],a
#line 45 "c:\users\iris\desktop\2. demo code\bh67f5362_24bit adc\Source\main.c"
	mov a,_ADCSourceData[2]
	mov _DrvUart0Format[3],a
#line 46 "c:\users\iris\desktop\2. demo code\bh67f5362_24bit adc\Source\main.c"
	mov a,_ADCSourceData[1]
	mov _DrvUart0Format[4],a
#line 47 "c:\users\iris\desktop\2. demo code\bh67f5362_24bit adc\Source\main.c"
	mov a,_ADCSourceData[0]
	mov _DrvUart0Format[5],a
#line 48 "c:\users\iris\desktop\2. demo code\bh67f5362_24bit adc\Source\main.c"
	clr _DrvUart0Format[6]
	mov a,6
	mov ra,a
#line 50 "c:\users\iris\desktop\2. demo code\bh67f5362_24bit adc\Source\main.c"
	clr rb
_L9:
#line 52 "c:\users\iris\desktop\2. demo code\bh67f5362_24bit adc\Source\main.c"
	mov a,low offset _DrvUart0Format
	add a,rb
	mov mp,a
	mov a,high offset _DrvUart0Format
	clr sbp
	adcm a,sbp
	fcall _Crom2Prom
	mov rc,a
	mov a,rc
	addm a,_DrvUart0Format[6]
#line 50 "c:\users\iris\desktop\2. demo code\bh67f5362_24bit adc\Source\main.c"
	inc rb
	sdz ra
	jmp _L9
#line 54 "c:\users\iris\desktop\2. demo code\bh67f5362_24bit adc\Source\main.c"
	mov a,7
	fcall _Drv_Uart0StartTx
_L7:
#pragma debug scope 2 1
#line 58 "c:\users\iris\desktop\2. demo code\bh67f5362_24bit adc\Source\main.c"
	snz _DrvUart0Format[116].1
	jmp _L11
#pragma debug scope 4 2
;begin block, line: 58.-1
#line 60 "c:\users\iris\desktop\2. demo code\bh67f5362_24bit adc\Source\main.c"
	clr _DrvUart0Format[116].1
	mov a,6
	mov rb,a
#line 61 "c:\users\iris\desktop\2. demo code\bh67f5362_24bit adc\Source\main.c"
	clr ra
#line 62 "c:\users\iris\desktop\2. demo code\bh67f5362_24bit adc\Source\main.c"
	clr rc
_L13:
#line 64 "c:\users\iris\desktop\2. demo code\bh67f5362_24bit adc\Source\main.c"
	mov a,low (offset _DrvUart0Format+100)
	add a,rc
	mov mp,a
	mov a,high (offset _DrvUart0Format+100)
	clr sbp
	adcm a,sbp
	fcall _Crom2Prom
	mov rd,a
	mov a,rd
	addm a,ra
#line 62 "c:\users\iris\desktop\2. demo code\bh67f5362_24bit adc\Source\main.c"
	inc rc
	sdz rb
	jmp _L13
#line 66 "c:\users\iris\desktop\2. demo code\bh67f5362_24bit adc\Source\main.c"
	mov a,ra
	sub a,_DrvUart0Format[106]
	snz z
	jmp _L11
#line 68 "c:\users\iris\desktop\2. demo code\bh67f5362_24bit adc\Source\main.c"
	mov a,_DrvUart0Format[100]
	mov _main_2[0],a
	mov a,_main_2[0]
	sub a,160
	sz z
	jmp _L14
	mov a,_main_2[0]
	sub a,161
	snz z
	jmp _L11
	jmp _L31
_L14:
#line 71 "c:\users\iris\desktop\2. demo code\bh67f5362_24bit adc\Source\main.c"
	mov a,_DrvUart0Format[103]
	mov ra,a
	mov a,ra
	mov _RegAddress[0],a
#line 72 "c:\users\iris\desktop\2. demo code\bh67f5362_24bit adc\Source\main.c"
	mov a,_DrvUart0Format[105]
	mov _RegData[0],a
#line 73 "c:\users\iris\desktop\2. demo code\bh67f5362_24bit adc\Source\main.c"
	mov a,17
	sub a,ra
	snz c
	jmp _L16
#line 74 "c:\users\iris\desktop\2. demo code\bh67f5362_24bit adc\Source\main.c"
	mov a,1
	mov _Status[0],a
	jmp _L17
_L16:
#line 77 "c:\users\iris\desktop\2. demo code\bh67f5362_24bit adc\Source\main.c"
	mov a,2
	mov _Status[0],a
_L17:
#line 79 "c:\users\iris\desktop\2. demo code\bh67f5362_24bit adc\Source\main.c"
	sdza _DrvUart0Format[101]
	jmp _L18
#line 80 "c:\users\iris\desktop\2. demo code\bh67f5362_24bit adc\Source\main.c"
	mov a,ra
	fcall _Drv_24BitADC_ReadReg
	mov ra,a
	mov a,ra
	mov _RegData[0],a
	jmp _L19
_L18:
#line 82 "c:\users\iris\desktop\2. demo code\bh67f5362_24bit adc\Source\main.c"
	mov a,_DrvUart0Format[101]
	sub a,2
	snz z
	jmp _L19
#line 83 "c:\users\iris\desktop\2. demo code\bh67f5362_24bit adc\Source\main.c"
	mov a,_RegData[0]
	mov _Drv_24BitADC_WriteReg_2[0],a
	mov a,ra
	fcall _Drv_24BitADC_WriteReg
_L19:
#line 86 "c:\users\iris\desktop\2. demo code\bh67f5362_24bit adc\Source\main.c"
	mov a,160
	mov _DrvUart0Format[0],a
#line 87 "c:\users\iris\desktop\2. demo code\bh67f5362_24bit adc\Source\main.c"
	mov a,_Status[0]
	mov ra,a
	mov a,ra
	mov _DrvUart0Format[1],a
#line 88 "c:\users\iris\desktop\2. demo code\bh67f5362_24bit adc\Source\main.c"
	clr _DrvUart0Format[2]
#line 89 "c:\users\iris\desktop\2. demo code\bh67f5362_24bit adc\Source\main.c"
	mov a,_RegAddress[0]
	mov rb,a
	mov a,rb
	mov _DrvUart0Format[3],a
#line 90 "c:\users\iris\desktop\2. demo code\bh67f5362_24bit adc\Source\main.c"
	clr _DrvUart0Format[4]
#line 91 "c:\users\iris\desktop\2. demo code\bh67f5362_24bit adc\Source\main.c"
	mov a,_RegData[0]
	mov rc,a
	mov a,rc
	mov _DrvUart0Format[5],a
#line 92 "c:\users\iris\desktop\2. demo code\bh67f5362_24bit adc\Source\main.c"
	mov a,160
	addm a,rc
	mov a,rb
	addm a,ra
	mov a,rc
	add a,ra
	mov _DrvUart0Format[6],a
	jmp _L28
_L31:
#line 96 "c:\users\iris\desktop\2. demo code\bh67f5362_24bit adc\Source\main.c"
	mov a,_DrvUart0Format[103]
	mov _CommandAddress[0],a
#line 97 "c:\users\iris\desktop\2. demo code\bh67f5362_24bit adc\Source\main.c"
	mov a,_DrvUart0Format[105]
	mov _main_2[0],a
	mov a,_main_2[0]
	mov _CommandData[0],a
#line 99 "c:\users\iris\desktop\2. demo code\bh67f5362_24bit adc\Source\main.c"
	mov a,2
	mov _Status[0],a
#line 100 "c:\users\iris\desktop\2. demo code\bh67f5362_24bit adc\Source\main.c"
	mov a,_CommandAddress[0]
	sub a,16
	snz z
	jmp _L20
	mov a,_DrvUart0Format[101]
	sub a,2
	snz z
	jmp _L20
#line 102 "c:\users\iris\desktop\2. demo code\bh67f5362_24bit adc\Source\main.c"
	mov a,_main_2[0]
	sub a,2
	snz z
	jmp _L21
#line 104 "c:\users\iris\desktop\2. demo code\bh67f5362_24bit adc\Source\main.c"
	fcall _Drv_24BitADC_Stop
	jmp _L29
_L21:
#line 107 "c:\users\iris\desktop\2. demo code\bh67f5362_24bit adc\Source\main.c"
	sdza _main_2[0]
	jmp _L20
#line 109 "c:\users\iris\desktop\2. demo code\bh67f5362_24bit adc\Source\main.c"
	fcall _Drv_24BitADC_Start
_L29:
#line 110 "c:\users\iris\desktop\2. demo code\bh67f5362_24bit adc\Source\main.c"
	mov a,1
	mov _Status[0],a
_L20:
#line 114 "c:\users\iris\desktop\2. demo code\bh67f5362_24bit adc\Source\main.c"
	mov a,161
	mov _DrvUart0Format[0],a
#line 115 "c:\users\iris\desktop\2. demo code\bh67f5362_24bit adc\Source\main.c"
	mov a,_Status[0]
	mov _DrvUart0Format[1],a
#line 116 "c:\users\iris\desktop\2. demo code\bh67f5362_24bit adc\Source\main.c"
	clr _DrvUart0Format[2]
#line 117 "c:\users\iris\desktop\2. demo code\bh67f5362_24bit adc\Source\main.c"
	mov a,_CommandAddress[0]
	mov ra,a
	mov a,ra
	mov _DrvUart0Format[3],a
#line 118 "c:\users\iris\desktop\2. demo code\bh67f5362_24bit adc\Source\main.c"
	clr _DrvUart0Format[4]
#line 119 "c:\users\iris\desktop\2. demo code\bh67f5362_24bit adc\Source\main.c"
	mov a,_CommandData[0]
	mov rb,a
	mov a,rb
	mov _DrvUart0Format[5],a
#line 120 "c:\users\iris\desktop\2. demo code\bh67f5362_24bit adc\Source\main.c"
	mov a,rb
	addm a,ra
	mov a,ra
	add a,161
	mov _DrvUart0Format[6],a
_L28:
#line 121 "c:\users\iris\desktop\2. demo code\bh67f5362_24bit adc\Source\main.c"
	mov a,7
	fcall _Drv_Uart0StartTx
#line 122 "c:\users\iris\desktop\2. demo code\bh67f5362_24bit adc\Source\main.c"
	jmp _L11
#pragma debug scope 2 1
	jmp $
_main endp

@dummy proc
	call _main
@dummy endp

#line 122 "c:\users\iris\desktop\2. demo code\bh67f5362_24bit adc\Source\main.c"
#pragma debug scope 1 1
#line 12 "c:\users\iris\desktop\2. demo code\bh67f5362_24bit adc\Source\main.c"
public _Status
@HCCINIT0_Status .section 'data'
_Status	db 0
#pragma debug variable 8 1 _Status "Status"

@HCCINIT .section 'data'
#line 11 "c:\users\iris\desktop\2. demo code\bh67f5362_24bit adc\Source\main.c"
public _CommandAddress
@HCCINIT0_CommandAddress .section 'data'
_CommandAddress	db 0
#pragma debug variable 8 1 _CommandAddress "CommandAddress"

@HCCINIT .section 'data'
#line 11 "c:\users\iris\desktop\2. demo code\bh67f5362_24bit adc\Source\main.c"
public _CommandData
@HCCINIT0_CommandData .section 'data'
_CommandData	db 0
#pragma debug variable 8 1 _CommandData "CommandData"

@HCCINIT .section 'data'
#line 10 "c:\users\iris\desktop\2. demo code\bh67f5362_24bit adc\Source\main.c"
public _RegAddress
@HCCINIT0_RegAddress .section 'data'
_RegAddress	db 0
#pragma debug variable 8 1 _RegAddress "RegAddress"

@HCCINIT .section 'data'
#line 10 "c:\users\iris\desktop\2. demo code\bh67f5362_24bit adc\Source\main.c"
public _RegData
@HCCINIT0_RegData .section 'data'
_RegData	db 0
#pragma debug variable 8 1 _RegData "RegData"

@HCCINIT .section 'data'
#pragma debug struct_begin 42 "__status_bits"
#pragma debug field 21 8 0 1 "__c" ;0,1
#pragma debug field 21 8 0 1 "__ac" ;1,1
#pragma debug field 21 8 0 1 "__z" ;2,1
#pragma debug field 21 8 0 1 "__ov" ;3,1
#pragma debug field 21 8 0 1 "__pdf" ;4,1
#pragma debug field 21 8 0 1 "__to" ;5,1
#pragma debug field 21 8 0 1 "__cz" ;6,1
#pragma debug field 21 8 0 1 "__sc" ;7,1
#pragma debug struct_end
#pragma debug union_begin 43 ""
#pragma debug field 2 42 "bits"
#pragma debug field 0 8 "byte"
#pragma debug union_end
#pragma debug variable 43 1 ___status "__status" 1
#pragma debug struct_begin 44 "__wdtc_bits"
#pragma debug field 21 8 0 1 "__ws0" ;0,1
#pragma debug field 21 8 0 1 "__ws1" ;1,1
#pragma debug field 21 8 0 1 "__ws2" ;2,1
#pragma debug field 21 8 0 1 "__we0" ;3,1
#pragma debug field 21 8 0 1 "__we1" ;4,1
#pragma debug field 21 8 0 1 "__we2" ;5,1
#pragma debug field 21 8 0 1 "__we3" ;6,1
#pragma debug field 21 8 0 1 "__we4" ;7,1
#pragma debug struct_end
#pragma debug union_begin 45 ""
#pragma debug field 2 44 "bits"
#pragma debug field 0 8 "byte"
#pragma debug union_end
#pragma debug variable 45 1 ___wdtc "__wdtc" 1
#pragma debug struct_begin 46 "__lvrc_bits"
#pragma debug field 21 8 0 1 "__lvs0" ;0,1
#pragma debug field 21 8 0 1 "__lvs1" ;1,1
#pragma debug field 21 8 0 1 "__lvs2" ;2,1
#pragma debug field 21 8 0 1 "__lvs3" ;3,1
#pragma debug field 21 8 0 1 "__lvs4" ;4,1
#pragma debug field 21 8 0 1 "__lvs5" ;5,1
#pragma debug field 21 8 0 1 "__lvs6" ;6,1
#pragma debug field 21 8 0 1 "__lvs7" ;7,1
#pragma debug struct_end
#pragma debug union_begin 47 ""
#pragma debug field 2 46 "bits"
#pragma debug field 0 8 "byte"
#pragma debug union_end
#pragma debug variable 47 1 ___lvrc "__lvrc" 1

; output external variables
extern _DrvUart0Format:byte
extern _ADCSourceData:byte
#line 14 "c:\users\iris\desktop\2. demo code\bh67f5362_24bit adc\Source\main.c"
@code .section at 0 'code'
	clr bp
	jmp _main_startup1

extern _Drv_SysClockInit:near
extern _Drv_RamInit:near
extern _Drv_UART0_Init:near
extern _Drv_24BitADC_Init:near
extern _Drv_24BitADC_Start:near
extern _Drv_24BitADC_ReadADCData:near
extern _Drv_Uart0StartTx:near
extern _Drv_24BitADC_ReadReg:near
extern _Drv_24BitADC_WriteReg_2:byte
extern _Drv_24BitADC_WriteReg:near
extern _Drv_24BitADC_Stop:near

; 
; Generated by holtek-gcc v3.20, Fri Aug 28 11:34:18 2020
; Rebuild 610
; end of file
