; Generated by holtek-gcc v3.20, Fri Aug 28 11:13:53 2020
; 
; Configuration:
;       with long instruction
;       Multi-ROM, Multi-RAM
;       bits_per_rom_unit:16
;       with mp1
;       with tbhp, address(0x9)
;          Use tabrd-const
;       
; SFR address of long-instruction arch:
;    mp0 = -1,1,0
;    mp1 = 4,3,2
;    mp2 = 14,13,12
;    tbp = 9,7,8
;    acc = 5
;    pcl = 6
;    status = 10
;    bp = 11
;    intc = 16
;       
;       
; use 'tabrdc' instead of 'tabrd'
;       

#pragma translator "holtek-gcc 4.6.4" "3.20" "build 20130711"
; Rebuild 610

ir equ [2]
mp equ [3]
sbp equ [4]
acc equ [5]
bp equ [11]
tblp equ [7]
tbhp equ [9]
status equ [10]
c equ [10].0
ac equ [10].1
z equ [10].2
ov equ [10].3
cz equ [10].6
sc equ [10].7
intc equ [16]
mduwr0 equ [59h]
mduwr1 equ [5ah]
mduwr2 equ [5bh]
mduwr3 equ [5ch]
mduwr4 equ [5dh]
mduwr5 equ [5eh]
mduwrctrl equ [5fh]

extern ra:byte
extern rb:byte
extern rc:byte
extern rd:byte
extern re:byte
extern rf:byte
extern rg:byte
extern rh:byte
extern _Crom2Prom:near
extern _Crom2PromNext:near

RAMBANK 0 @BITDATASEC, @BITDATASEC1
@HCCINIT	.section 'data'
@HCCINIT0	.section 'data'
@BITDATASEC	 .section 'data'
@BITDATASEC1	 .section 'data'

#pragma debug scope 1 1
	extern __DELAY3:near
	extern __DELAYX3:near
	extern __DELAYX6:near
	extern __DELAYY5:near
	extern __DELAYY3:near
	extern _builtin_holtek_delay_2:byte
___pas1 equ [335]
___ifs2 equ [331]
___sima equ [111]
___simc0 equ [108]
___simc1 equ [109]
___simtoc equ [112]
___mfi3 equ [73]
___intc2 equ [18]
___intc0 equ [16]
public _Drv_SIM_PowerOn
#pragma debug scope 2 1
#line 27 "C:\Users\iris\Desktop\2. demo code\BH67F5362_SIMIIC\BH67F5362_Drv\Drv_SIM.c"
_Drv_SIM_PowerOn .section 'code'
_Drv_SIM_PowerOn proc
#line 29 "C:\Users\iris\Desktop\2. demo code\BH67F5362_SIMIIC\BH67F5362_Drv\Drv_SIM.c"
	lclr [335].3
	lset [335].2
	lclr [331].4
#line 30 "C:\Users\iris\Desktop\2. demo code\BH67F5362_SIMIIC\BH67F5362_Drv\Drv_SIM.c"
	lclr [335].1
	lset [335].0
	lclr [331].5
#line 31 "C:\Users\iris\Desktop\2. demo code\BH67F5362_SIMIIC\BH67F5362_Drv\Drv_SIM.c"
	mov a,160
	mov [111],a
#line 32 "C:\Users\iris\Desktop\2. demo code\BH67F5362_SIMIIC\BH67F5362_Drv\Drv_SIM.c"
	mov a,196
	mov [108],a
#line 33 "C:\Users\iris\Desktop\2. demo code\BH67F5362_SIMIIC\BH67F5362_Drv\Drv_SIM.c"
	mov a,2
	mov [109],a
#line 34 "C:\Users\iris\Desktop\2. demo code\BH67F5362_SIMIIC\BH67F5362_Drv\Drv_SIM.c"
	mov a,192
	mov [112],a
#line 35 "C:\Users\iris\Desktop\2. demo code\BH67F5362_SIMIIC\BH67F5362_Drv\Drv_SIM.c"
	set [108].1
	clr [73].7
	set [73].3
#line 44 "C:\Users\iris\Desktop\2. demo code\BH67F5362_SIMIIC\BH67F5362_Drv\Drv_SIM.c"
	clr [18].7
#line 45 "C:\Users\iris\Desktop\2. demo code\BH67F5362_SIMIIC\BH67F5362_Drv\Drv_SIM.c"
	set [18].3
#line 46 "C:\Users\iris\Desktop\2. demo code\BH67F5362_SIMIIC\BH67F5362_Drv\Drv_SIM.c"
	set [16].0
	ret
_Drv_SIM_PowerOn endp
#line 46 "C:\Users\iris\Desktop\2. demo code\BH67F5362_SIMIIC\BH67F5362_Drv\Drv_SIM.c"
#pragma debug scope 1 1
public _Drv_SIM_PowerDown
#pragma debug scope 3 1
#line 53 "C:\Users\iris\Desktop\2. demo code\BH67F5362_SIMIIC\BH67F5362_Drv\Drv_SIM.c"
_Drv_SIM_PowerDown .section 'code'
_Drv_SIM_PowerDown proc
#line 56 "C:\Users\iris\Desktop\2. demo code\BH67F5362_SIMIIC\BH67F5362_Drv\Drv_SIM.c"
	clr [108].1
#line 57 "C:\Users\iris\Desktop\2. demo code\BH67F5362_SIMIIC\BH67F5362_Drv\Drv_SIM.c"
	clr [73].3
	clr [73].7
	ret
_Drv_SIM_PowerDown endp
#line 57 "C:\Users\iris\Desktop\2. demo code\BH67F5362_SIMIIC\BH67F5362_Drv\Drv_SIM.c"
#pragma debug scope 1 1
___simd equ [110]
___acc equ [5]
public _SIM_ISR
#pragma debug scope 4 1
#line 72 "C:\Users\iris\Desktop\2. demo code\BH67F5362_SIMIIC\BH67F5362_Drv\Drv_SIM.c"
rombank 0 @SIM_ISR_code
@SIM_ISR_code .section at 44 'code'
	mov r1,a
	mov a,bp
	clr bp
	jmp _SIM_ISR
ROMBANK 0 _SIM_ISR
#pragma debug scope 1 1
@dummy44 proc
	call _SIM_ISR
@dummy44 endp
#pragma debug scope 5 1
_SIM_ISR .section 'code'
_SIM_ISR proc
	mov r2,a
	mov a, status
	mov r3,a
	mov a,mp
	mov r4,a
	mov a,sbp
	mov r5,a
	mov a,tblp
	mov r6,a
	mov a,tbhp
	mov r7,a
#line 75 "C:\Users\iris\Desktop\2. demo code\BH67F5362_SIMIIC\BH67F5362_Drv\Drv_SIM.c"
	clr [73].7
#line 76 "C:\Users\iris\Desktop\2. demo code\BH67F5362_SIMIIC\BH67F5362_Drv\Drv_SIM.c"
	snz [112].6
	jmp _L4
#line 78 "C:\Users\iris\Desktop\2. demo code\BH67F5362_SIMIIC\BH67F5362_Drv\Drv_SIM.c"
	clr [112].6
#line 79 "C:\Users\iris\Desktop\2. demo code\BH67F5362_SIMIIC\BH67F5362_Drv\Drv_SIM.c"
	set [112].7
#line 80 "C:\Users\iris\Desktop\2. demo code\BH67F5362_SIMIIC\BH67F5362_Drv\Drv_SIM.c"
	set [109].1
#line 81 "C:\Users\iris\Desktop\2. demo code\BH67F5362_SIMIIC\BH67F5362_Drv\Drv_SIM.c"
	clr _SIM_Data[40]
	jmp _L24
_L4:
#line 86 "C:\Users\iris\Desktop\2. demo code\BH67F5362_SIMIIC\BH67F5362_Drv\Drv_SIM.c"
	snz [109].6
	jmp _L6
	snz [109].2
	jmp _L6
#line 88 "C:\Users\iris\Desktop\2. demo code\BH67F5362_SIMIIC\BH67F5362_Drv\Drv_SIM.c"
	set [109].4
#line 89 "C:\Users\iris\Desktop\2. demo code\BH67F5362_SIMIIC\BH67F5362_Drv\Drv_SIM.c"
	clr _SIM_Data[41]
#line 90 "C:\Users\iris\Desktop\2. demo code\BH67F5362_SIMIIC\BH67F5362_Drv\Drv_SIM.c"
	mov a,low (offset _SIM_Data+20)
	add a,_SIM_Data[41]
	mov mp,a
	mov a,high (offset _SIM_Data+20)
	clr sbp
	adcm a,sbp
	fcall _Crom2Prom
	mov [110],a
#line 91 "C:\Users\iris\Desktop\2. demo code\BH67F5362_SIMIIC\BH67F5362_Drv\Drv_SIM.c"
	inc _SIM_Data[41]
	jmp _L3
_L6:
#line 93 "C:\Users\iris\Desktop\2. demo code\BH67F5362_SIMIIC\BH67F5362_Drv\Drv_SIM.c"
	snz [109].6
	jmp _L7
	sz [109].2
	jmp _L7
#line 95 "C:\Users\iris\Desktop\2. demo code\BH67F5362_SIMIIC\BH67F5362_Drv\Drv_SIM.c"
	clr [109].4
#line 96 "C:\Users\iris\Desktop\2. demo code\BH67F5362_SIMIIC\BH67F5362_Drv\Drv_SIM.c"
	clr [109].3
#line 97 "C:\Users\iris\Desktop\2. demo code\BH67F5362_SIMIIC\BH67F5362_Drv\Drv_SIM.c"
	mov a,low offset _SIM_Data
	add a,_SIM_Data[40]
	mov mp,a
	mov a,high offset _SIM_Data
	clr sbp
	adcm a,sbp
	mov a,[110]
	mov ir,a
#line 98 "C:\Users\iris\Desktop\2. demo code\BH67F5362_SIMIIC\BH67F5362_Drv\Drv_SIM.c"
	inc _SIM_Data[40]
	jmp _L3
_L7:
#line 105 "C:\Users\iris\Desktop\2. demo code\BH67F5362_SIMIIC\BH67F5362_Drv\Drv_SIM.c"
	sz [109].6
	jmp _L8
	snz [109].4
	jmp _L8
#line 107 "C:\Users\iris\Desktop\2. demo code\BH67F5362_SIMIIC\BH67F5362_Drv\Drv_SIM.c"
	snz [109].0
	jmp _L9
#line 109 "C:\Users\iris\Desktop\2. demo code\BH67F5362_SIMIIC\BH67F5362_Drv\Drv_SIM.c"
	clr [109].4
#line 110 "C:\Users\iris\Desktop\2. demo code\BH67F5362_SIMIIC\BH67F5362_Drv\Drv_SIM.c"
	clr [109].3
#line 111 "C:\Users\iris\Desktop\2. demo code\BH67F5362_SIMIIC\BH67F5362_Drv\Drv_SIM.c"
	mov a,[110]
	mov [5],a
	jmp _L3
_L9:
#line 115 "C:\Users\iris\Desktop\2. demo code\BH67F5362_SIMIIC\BH67F5362_Drv\Drv_SIM.c"
	mov a,low (offset _SIM_Data+20)
	add a,_SIM_Data[41]
	mov mp,a
	mov a,high (offset _SIM_Data+20)
	clr sbp
	adcm a,sbp
	fcall _Crom2Prom
	mov [110],a
#line 116 "C:\Users\iris\Desktop\2. demo code\BH67F5362_SIMIIC\BH67F5362_Drv\Drv_SIM.c"
	inc _SIM_Data[41]
#line 117 "C:\Users\iris\Desktop\2. demo code\BH67F5362_SIMIIC\BH67F5362_Drv\Drv_SIM.c"
	mov a,3
	sub a,_SIM_Data[41]
	sz c
	jmp _L3
_L24:
#line 119 "C:\Users\iris\Desktop\2. demo code\BH67F5362_SIMIIC\BH67F5362_Drv\Drv_SIM.c"
	clr _SIM_Data[41]
	jmp _L3
_L8:
#line 123 "C:\Users\iris\Desktop\2. demo code\BH67F5362_SIMIIC\BH67F5362_Drv\Drv_SIM.c"
	sz [109].6
	jmp _L3
	sz [109].4
	jmp _L3
#line 125 "C:\Users\iris\Desktop\2. demo code\BH67F5362_SIMIIC\BH67F5362_Drv\Drv_SIM.c"
	mov a,low offset _SIM_Data
	add a,_SIM_Data[40]
	mov mp,a
	mov a,high offset _SIM_Data
	clr sbp
	adcm a,sbp
	mov a,[110]
	mov ir,a
#line 126 "C:\Users\iris\Desktop\2. demo code\BH67F5362_SIMIIC\BH67F5362_Drv\Drv_SIM.c"
	inc _SIM_Data[40]
#line 127 "C:\Users\iris\Desktop\2. demo code\BH67F5362_SIMIIC\BH67F5362_Drv\Drv_SIM.c"
	mov a,3
	sub a,_SIM_Data[40]
	sz c
	jmp _L3
#line 129 "C:\Users\iris\Desktop\2. demo code\BH67F5362_SIMIIC\BH67F5362_Drv\Drv_SIM.c"
	clr _SIM_Data[40]
#line 130 "C:\Users\iris\Desktop\2. demo code\BH67F5362_SIMIIC\BH67F5362_Drv\Drv_SIM.c"
	set _SIM_Data[45].1
_L3:
	mov a,r2
	mov bp,a
	mov a,r3
	mov status,a
	mov a,r4
	mov mp,a
	mov a,r5
	mov sbp,a
	mov a,r6
	mov tblp,a
	mov a,r7
	mov tbhp,a
	tabrdc acc
	mov a,r1
	reti
_SIM_ISR endp

#line 130 "C:\Users\iris\Desktop\2. demo code\BH67F5362_SIMIIC\BH67F5362_Drv\Drv_SIM.c"
#pragma debug scope 1 1
___simc2 equ [111]
public _Drv_SIMSPI_TxRxByte
#pragma debug scope 6 1
#line 165 "C:\Users\iris\Desktop\2. demo code\BH67F5362_SIMIIC\BH67F5362_Drv\Drv_SIM.c"
_Drv_SIMSPI_TxRxByte .section 'code'
_Drv_SIMSPI_TxRxByte proc
    local _Drv_SIMSPI_TxRxByte_2 db 1 dup(?)	; 0,1
	mov _Drv_SIMSPI_TxRxByte_2[0],a
#pragma debug variable 8 6 _Drv_SIMSPI_TxRxByte_2+0 "txData"
_L29:
#line 167 "C:\Users\iris\Desktop\2. demo code\BH67F5362_SIMIIC\BH67F5362_Drv\Drv_SIM.c"
	clr [111].1
#line 168 "C:\Users\iris\Desktop\2. demo code\BH67F5362_SIMIIC\BH67F5362_Drv\Drv_SIM.c"
;# 168 "C:\Users\iris\Desktop\2. demo code\BH67F5362_SIMIIC\BH67F5362_Drv\Drv_SIM.c" 1
	clr wdt
#line 169 "C:\Users\iris\Desktop\2. demo code\BH67F5362_SIMIIC\BH67F5362_Drv\Drv_SIM.c"
	mov a,_Drv_SIMSPI_TxRxByte_2[0]
	mov [110],a
#line 171 "C:\Users\iris\Desktop\2. demo code\BH67F5362_SIMIIC\BH67F5362_Drv\Drv_SIM.c"
	sz [111].1
	jmp _L29
_L28:
#line 172 "C:\Users\iris\Desktop\2. demo code\BH67F5362_SIMIIC\BH67F5362_Drv\Drv_SIM.c"
	sz [111].0
	jmp _L31
#line 174 "C:\Users\iris\Desktop\2. demo code\BH67F5362_SIMIIC\BH67F5362_Drv\Drv_SIM.c"
;# 174 "C:\Users\iris\Desktop\2. demo code\BH67F5362_SIMIIC\BH67F5362_Drv\Drv_SIM.c" 1
	clr wdt
	jmp _L28
_L31:
#line 176 "C:\Users\iris\Desktop\2. demo code\BH67F5362_SIMIIC\BH67F5362_Drv\Drv_SIM.c"
	clr [111].0
#line 177 "C:\Users\iris\Desktop\2. demo code\BH67F5362_SIMIIC\BH67F5362_Drv\Drv_SIM.c"
	mov a,[110]
	mov ra,a
#line 178 "C:\Users\iris\Desktop\2. demo code\BH67F5362_SIMIIC\BH67F5362_Drv\Drv_SIM.c"
	mov a,ra
	ret
_Drv_SIMSPI_TxRxByte endp
#line 178 "C:\Users\iris\Desktop\2. demo code\BH67F5362_SIMIIC\BH67F5362_Drv\Drv_SIM.c"
#pragma debug scope 1 1
public _Drv_SIMSPI_TxRxBuf
#pragma debug scope 7 1
#line 181 "C:\Users\iris\Desktop\2. demo code\BH67F5362_SIMIIC\BH67F5362_Drv\Drv_SIM.c"
_Drv_SIMSPI_TxRxBuf .section 'code'
_Drv_SIMSPI_TxRxBuf proc
public _Drv_SIMSPI_TxRxBuf_2
    local _Drv_SIMSPI_TxRxBuf_2 db 6 dup(?)	; 2,4
	mov _Drv_SIMSPI_TxRxBuf_2[2],a
#pragma debug variable 8 7 _Drv_SIMSPI_TxRxBuf_2+2 "len"
#pragma debug pointer 42 8 7
#pragma debug variable 42 7 _Drv_SIMSPI_TxRxBuf_2+0 "txBuf"
#pragma debug variable 8 7 _Drv_SIMSPI_TxRxBuf_2+3 "i"
#line 183 "C:\Users\iris\Desktop\2. demo code\BH67F5362_SIMIIC\BH67F5362_Drv\Drv_SIM.c"
	clr _Drv_SIMSPI_TxRxBuf_2[3]
	jmp _L33
_L34:
#line 185 "C:\Users\iris\Desktop\2. demo code\BH67F5362_SIMIIC\BH67F5362_Drv\Drv_SIM.c"
	mov a,_Drv_SIMSPI_TxRxBuf_2[3]
	mov _Drv_SIMSPI_TxRxBuf_2[4],a
	clr _Drv_SIMSPI_TxRxBuf_2[5]
	mov a,_Drv_SIMSPI_TxRxBuf_2[4]
	add a,_Drv_SIMSPI_TxRxBuf_2[0]
	mov mp,a
	mov a,_Drv_SIMSPI_TxRxBuf_2[5]
	adc a,_Drv_SIMSPI_TxRxBuf_2[1]
	mov sbp,a
	fcall _Crom2Prom
	mov ra,a
	mov a,ra
	fcall _Drv_SIMSPI_TxRxByte
	mov ra,a
	mov a,low offset _SIM_Data
	add a,_Drv_SIMSPI_TxRxBuf_2[4]
	mov mp,a
	mov a,high offset _SIM_Data
	adc a,_Drv_SIMSPI_TxRxBuf_2[5]
	mov sbp,a
	mov a,ra
	mov ir,a
#line 186 "C:\Users\iris\Desktop\2. demo code\BH67F5362_SIMIIC\BH67F5362_Drv\Drv_SIM.c"
	clr [73].7
#line 183 "C:\Users\iris\Desktop\2. demo code\BH67F5362_SIMIIC\BH67F5362_Drv\Drv_SIM.c"
	inc _Drv_SIMSPI_TxRxBuf_2[3]
_L33:
	mov a,_Drv_SIMSPI_TxRxBuf_2[3]
	sub a,_Drv_SIMSPI_TxRxBuf_2[2]
	snz c
	jmp _L34
	ret
_Drv_SIMSPI_TxRxBuf endp
#line 183 "C:\Users\iris\Desktop\2. demo code\BH67F5362_SIMIIC\BH67F5362_Drv\Drv_SIM.c"
#pragma debug scope 1 1
#line 20 "C:\Users\iris\Desktop\2. demo code\BH67F5362_SIMIIC\BH67F5362_Drv\Drv_SIM.c"
public _SIM_Data
@HCCINIT0_SIM_Data .section 'data'
_SIM_Data	db 46 dup(0)
#pragma debug struct_begin 43 ""
#pragma debug field 21 8 0 1 "TxIsBusy" ;0,1
#pragma debug field 21 8 0 1 "RxIsOK" ;1,1
#pragma debug struct_end
#pragma debug union_begin 44 ""
#pragma debug field 2 43 "b"
#pragma debug field 0 8 "byte"
#pragma debug union_end
#pragma debug struct_begin 45 ""
#pragma debug field 1 8 20 "RxBuf"
#pragma debug field 1 8 20 "TxBuf"
#pragma debug field 0 8 "RxOffset"
#pragma debug field 0 8 "TxOffset"
#pragma debug field 0 8 "RxLength"
#pragma debug field 0 8 "TxLength"
#pragma debug field 0 8 "RxTimeOut"
#pragma debug field 3 44 "flag"
#pragma debug struct_end
#pragma debug variable 45 1 _SIM_Data "SIM_Data"

@HCCINIT .section 'data'
#pragma debug variable 8 1 ___acc "__acc" 1
#pragma debug struct_begin 46 "__intc0_bits"
#pragma debug field 21 8 0 1 "__emi" ;0,1
#pragma debug field 21 8 0 1 "__int0e" ;1,1
#pragma debug field 21 8 0 1 "__int1e" ;2,1
#pragma debug field 21 8 0 1 "__mf6e" ;3,1
#pragma debug field 21 8 0 1 "__int0f" ;4,1
#pragma debug field 21 8 0 1 "__int1f" ;5,1
#pragma debug field 21 8 0 1 "__mf6f" ;6,1
#pragma debug field 21 8 0 1 ;7,1
#pragma debug struct_end
#pragma debug union_begin 47 ""
#pragma debug field 2 46 "bits"
#pragma debug field 0 8 "byte"
#pragma debug union_end
#pragma debug variable 47 1 ___intc0 "__intc0" 1
#pragma debug struct_begin 48 "__intc2_bits"
#pragma debug field 21 8 0 1 "__mf2e" ;0,1
#pragma debug field 21 8 0 1 "__mf8e" ;1,1
#pragma debug field 21 8 0 1 "__mf9e" ;2,1
#pragma debug field 21 8 0 1 "__mf3e" ;3,1
#pragma debug field 21 8 0 1 "__mf2f" ;4,1
#pragma debug field 21 8 0 1 "__mf8f" ;5,1
#pragma debug field 21 8 0 1 "__mf9f" ;6,1
#pragma debug field 21 8 0 1 "__mf3f" ;7,1
#pragma debug struct_end
#pragma debug union_begin 49 ""
#pragma debug field 2 48 "bits"
#pragma debug field 0 8 "byte"
#pragma debug union_end
#pragma debug variable 49 1 ___intc2 "__intc2" 1
#pragma debug struct_begin 50 "__mfi3_bits"
#pragma debug field 21 8 0 1 "__lve" ;0,1
#pragma debug field 21 8 0 1 "__dee" ;1,1
#pragma debug field 21 8 0 1 "__spie" ;2,1
#pragma debug field 21 8 0 1 "__sime" ;3,1
#pragma debug field 21 8 0 1 "__lvf" ;4,1
#pragma debug field 21 8 0 1 "__def" ;5,1
#pragma debug field 21 8 0 1 "__spif" ;6,1
#pragma debug field 21 8 0 1 "__simf" ;7,1
#pragma debug struct_end
#pragma debug union_begin 51 ""
#pragma debug field 2 50 "bits"
#pragma debug field 0 8 "byte"
#pragma debug union_end
#pragma debug variable 51 1 ___mfi3 "__mfi3" 1
#pragma debug struct_begin 52 "__simc0_bits"
#pragma debug field 21 8 0 1 "__simicf" ;0,1
#pragma debug field 21 8 0 1 "__simen" ;1,1
#pragma debug field 21 8 0 1 "__simdeb0" ;2,1
#pragma debug field 21 8 0 1 "__simdeb1" ;3,1
#pragma debug field 21 8 0 1 ;4,1
#pragma debug field 21 8 0 1 "__sim0" ;5,1
#pragma debug field 21 8 0 1 "__sim1" ;6,1
#pragma debug field 21 8 0 1 "__sim2" ;7,1
#pragma debug struct_end
#pragma debug union_begin 53 ""
#pragma debug field 2 52 "bits"
#pragma debug field 0 8 "byte"
#pragma debug union_end
#pragma debug variable 53 1 ___simc0 "__simc0" 1
#pragma debug struct_begin 54 "__simc1_bits"
#pragma debug field 21 8 0 1 "__rxak" ;0,1
#pragma debug field 21 8 0 1 "__iamwu" ;1,1
#pragma debug field 21 8 0 1 "__srw" ;2,1
#pragma debug field 21 8 0 1 "__txak" ;3,1
#pragma debug field 21 8 0 1 "__htx" ;4,1
#pragma debug field 21 8 0 1 "__hbb" ;5,1
#pragma debug field 21 8 0 1 "__haas" ;6,1
#pragma debug field 21 8 0 1 "__hcf" ;7,1
#pragma debug struct_end
#pragma debug union_begin 55 ""
#pragma debug field 2 54 "bits"
#pragma debug field 0 8 "byte"
#pragma debug union_end
#pragma debug variable 55 1 ___simc1 "__simc1" 1
#pragma debug variable 8 1 ___simd "__simd" 1
#pragma debug struct_begin 56 "__simc2_bits"
#pragma debug field 21 8 0 1 "__trf" ;0,1
#pragma debug field 21 8 0 1 "__wcol" ;1,1
#pragma debug field 21 8 0 1 "__csen" ;2,1
#pragma debug field 21 8 0 1 "__mls" ;3,1
#pragma debug field 21 8 0 1 "__ckeg" ;4,1
#pragma debug field 21 8 0 1 "__ckpolb" ;5,1
#pragma debug field 21 8 0 2 ;6,2
#pragma debug struct_end
#pragma debug union_begin 57 ""
#pragma debug field 2 56 "bits"
#pragma debug field 0 8 "byte"
#pragma debug union_end
#pragma debug variable 57 1 ___simc2 "__simc2" 1
#pragma debug struct_begin 58 "__sima_bits"
#pragma debug field 21 8 0 1 ;0,1
#pragma debug field 21 8 0 1 "__sima0" ;1,1
#pragma debug field 21 8 0 1 "__sima1" ;2,1
#pragma debug field 21 8 0 1 "__sima2" ;3,1
#pragma debug field 21 8 0 1 "__sima3" ;4,1
#pragma debug field 21 8 0 1 "__sima4" ;5,1
#pragma debug field 21 8 0 1 "__sima5" ;6,1
#pragma debug field 21 8 0 1 "__sima6" ;7,1
#pragma debug struct_end
#pragma debug union_begin 59 ""
#pragma debug field 2 58 "bits"
#pragma debug field 0 8 "byte"
#pragma debug union_end
#pragma debug variable 59 1 ___sima "__sima" 1
#pragma debug struct_begin 60 "__simtoc_bits"
#pragma debug field 21 8 0 1 "__simtos0" ;0,1
#pragma debug field 21 8 0 1 "__simtos1" ;1,1
#pragma debug field 21 8 0 1 "__simtos2" ;2,1
#pragma debug field 21 8 0 1 "__simtos3" ;3,1
#pragma debug field 21 8 0 1 "__simtos4" ;4,1
#pragma debug field 21 8 0 1 "__simtos5" ;5,1
#pragma debug field 21 8 0 1 "__simtof" ;6,1
#pragma debug field 21 8 0 1 "__simtoen" ;7,1
#pragma debug struct_end
#pragma debug union_begin 61 ""
#pragma debug field 2 60 "bits"
#pragma debug field 0 8 "byte"
#pragma debug union_end
#pragma debug variable 61 1 ___simtoc "__simtoc" 1
#pragma debug struct_begin 62 "__ifs2_bits"
#pragma debug field 21 8 0 1 "__int0ps" ;0,1
#pragma debug field 21 8 0 1 "__int1ps" ;1,1
#pragma debug field 21 8 0 1 "__int2ps" ;2,1
#pragma debug field 21 8 0 1 "__int3ps" ;3,1
#pragma debug field 21 8 0 1 "__scksclps" ;4,1
#pragma debug field 21 8 0 1 "__sdisdaps" ;5,1
#pragma debug field 21 8 0 1 "__scsbps" ;6,1
#pragma debug field 21 8 0 1 ;7,1
#pragma debug struct_end
#pragma debug union_begin 63 ""
#pragma debug field 2 62 "bits"
#pragma debug field 0 8 "byte"
#pragma debug union_end
#pragma debug variable 63 1 ___ifs2 "__ifs2" 1
#pragma debug struct_begin 64 "__pas1_bits"
#pragma debug field 21 8 0 1 "__pas10" ;0,1
#pragma debug field 21 8 0 1 "__pas11" ;1,1
#pragma debug field 21 8 0 1 "__pas12" ;2,1
#pragma debug field 21 8 0 1 "__pas13" ;3,1
#pragma debug field 21 8 0 1 "__pas14" ;4,1
#pragma debug field 21 8 0 1 "__pas15" ;5,1
#pragma debug field 21 8 0 1 "__pas16" ;6,1
#pragma debug field 21 8 0 1 "__pas17" ;7,1
#pragma debug struct_end
#pragma debug union_begin 65 ""
#pragma debug field 2 64 "bits"
#pragma debug field 0 8 "byte"
#pragma debug union_end
#pragma debug variable 65 1 ___pas1 "__pas1" 1
extern r1:byte
extern r2:byte
extern r3:byte
extern r4:byte
extern r5:byte
extern r6:byte
extern r7:byte

; 
; Generated by holtek-gcc v3.20, Fri Aug 28 11:13:54 2020
; Rebuild 610
; end of file
